1. Field
Embodiments described herein relate generally to a semiconductor memory device and a method of operating the semiconductor memory device.
2. Description of the Related Art
In recent years, resistance varying memory devices employing a variable resistor as a memory element are attracting attention as candidates to succeed flash memory. The resistance varying memory devices are assumed here to include not only the narrowly-defined resistance varying memory (ReRAM: Resistive RAM), in which a transition metal oxide is used as a recording layer to store a resistance state of the transition metal oxide in a non-volatile manner, but also the likes of phase change memory (PCRAM: Phase Change RAM), in which chalcogenide or the like is used as a recording layer to utilize resistance information of a crystalline state (conductor) and an amorphous state (insulator).
There are known to be two kinds of operation modes in memory cells of a resistance varying memory device. In one, referred to as bipolar type, the polarity of applied voltage is switched to set a high-resistance state and a low-resistance state. In the other, referred to as unipolar type, the voltage value and voltage application time are controlled, thus allowing the high-resistance state and the low-resistance state to be set without switching the polarity of applied voltage.
This is explained as follows taking the case of unipolar type ReRAM as an example. Write of data to the memory cell is performed by applying a certain voltage to the variable resistor for a short time. This causes the variable resistor to change from the high-resistance state to the low-resistance state. This operation to change the variable resistor from the high-resistance state to the low-resistance state is hereinafter referred to as a setting operation. On the other hand, erase of data in the memory cell is performed by applying a certain voltage to the variable resistor for a long time, the certain voltage being lower than that applied during the setting operation, and the variable resistor being in the low-resistance state subsequent to the setting operation. This causes the variable resistor to change from the low-resistance state to the high-resistance state. This operation to change the variable resistor from the low-resistance state to the high-resistance state is hereinafter referred to as a resetting operation. The memory cell adopts, for example, the high-resistance state as a stable state (reset state), and, in the case of binary data storage, write of data is performed by the setting operation in which the reset state is changed to the low-resistance state.
Now, in the case that an operation is executed on the memory cell to change its resistance state, application of the operation voltage must be suspended subsequent to the resistance state of the variable resistor in the memory cell changing. Detection of change in the resistance value of the variable resistor is ordinarily performed using the change in the cell current flowing in the memory cell. Conventionally, a certain reference current is prepared, and the change in the resistance value of an element is detected by detecting that magnitudes of the current value of the cell current flowing in the element and the current value of the reference current are reversed. It is difficult to achieve uniformity in characteristics of variable resistors employed in memory cells, and the resistance value of a variable resistor subsequent to an operation varies for each memory cell. The reference current must be determined with a considerable margin, taking dispersion in the resistance value of the variable resistors into consideration. This leads to difficulties in determining the reference current employed for detecting whether or not the resistance state of a selected memory cell has shifted. There is a problem that, when the current value of the reference current deviates from that of the cell current flowing in the selected memory cell prior and subsequent to the operation, change in the resistance state cannot be detected, and the operation cannot be terminated normally.